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CY62157EV18 mobl ? 8-mbit (512k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05490 rev. *h revised june 29, 2011 8-bit (512k x 16) static ram features very high speed: 55 ns wide voltage range: 1.65 v?2.25 v pin compatible with cy62157dv18 and cy62157dv20 ultra low standby power ? typical standby current: 2 ? a ? maximum standby current: 8 ? a ultra low active power ? typical active current: 1.8 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 48-ball very fine-pitch ball grid array (vfbga) package functional description the CY62157EV18 is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provid e ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce 1 high or ce 2 low) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) or write operation is active (ce 1 low, ce 2 high and we low). write to the device by taking chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location spec ified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). read from the device by taking chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the ?truth table? on page 11 for a complete description of read and write modes. product portfolio product v cc range (v) speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( ? a) f = 1mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max CY62157EV18 1.65 1.8 2.25 55 1.8 3 18 25 2 8 note 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. www..net
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 2 of 16 logic block diagram 512k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 bhe ble a 10 a 18 power down circuit ce 2 ce 1 ce 2 ce 1
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 3 of 16 contents pin configuration ............................................................. 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 5 thermal resistance.......................................................... 6 ac test loads and waveforms ....................................... 6 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ..................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history ........................................................... 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 4 of 16 pin configuration [2] note 2. nc pins are not connected on the die. we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss 48-ball vfbga top view
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 5 of 16 maximum ratings exceeding maximum ratings may shor ten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential ............................?0.2 v to 2.45 v (v ccmax + 0.2 v) dc voltage applied to outputs in high-z state [3, 4] ...........?0.2 v to 2.45 v (v ccmax + 0.2 v) dc input voltage [3, 4] ....... ?0.2 v to 2.45 v (v ccmax + 0.2 v) output current into outputs (low) ............................. 20 ma static discharge voltage ......................................... > 2001 v (in accordance with mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range device range ambient temperature v cc [5] CY62157EV18ll industrial ?40 c to +85 c 1.65 v to 2.25 v electrical characteristics (over the operating range) parameter description test conditions 55 ns unit min typ [6] max v oh output high voltage i oh = ?0.1 ma v cc = 1.65 v 1.4 ? ? v v ol output low voltage i ol = 0.1 ma v cc = 1.65 v ? ? 0.2 v v ih input high voltage v cc = 1.65 v to 2.25 v 1.4 ? v cc + 0.2 v v v il input low voltage v cc = 1.65 v to 2.25 v ?0.2 ? 0.4 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?18 25ma f = 1 mhz ? 1.8 3 ma i sb1 [7] automatic ce power down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v v in > v cc ? 0.2 v, v in < 0.2 v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = v cc(max) . ?2 8 ? a i sb2 [7] automatic ce power down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) . ?2 8 ? a capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 3. v il(min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih(max) = v cc + 0.5 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 7. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 /i sb2 /i ccdr spec. other inputs can be left floating. 8. tested initially and after any design or proce ss changes that may affect these parameters.
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 6 of 16 thermal resistance parameter [9] description test conditions bga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 72 ? c/w ? jc thermal resistance (junction to case) 8.86 ? c/w ac test loads and waveforms parameters value unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v data retention characteristics (over the operating range) parameter description conditions min typ [10] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [11] data retention current v cc = v dr , ce 1 > v cc ? 0.2 v, ce 2 < 0.2 v,v in > v cc ? 0.2 v or v in < 0.2 v ?13 ? a t cdr [9] chip deselect to data retention time 0 ? ? ns t r [12] operation recovery time 55 ? ? ns data retention waveform [13] 3v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 v cc(min) t cdr v dr > 1.0v data retention mode t r v cc(min) ce 1 or v cc bhe .ble ce 2 or notes 9. tested initially and after any design or proce ss changes that may affect these parameters. 10. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 /i sb2 /i ccdr spec. other inputs can be left floating. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 13. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling ch ip enable signals or by disabling both bhe and ble .
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 7 of 16 switching characteristics (over the operating range) parameter [14, 15 ] description 55 ns unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low-z [16] 5 ? ns t hzoe oe high to high-z [16, 17] ? 18 ns t lzce ce 1 low and ce 2 high to low-z [16] 10 ? ns t hzce ce 1 high and ce 2 low to high-z [16, 17] ? 18 ns t pu ce 1 low and ce 2 high to power up 0 ? ns t pd ce 1 high and ce 2 low to power down ? 55 ns t dbe ble /bhe low to data valid ? 55 ns t lzbe [18] ble /bhe low to low-z [16] 10 ? ns t hzbe ble /bhe high to high-z [16, 17] ? 18 ns write cycle [19] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high-z [16, 17] ? 18 ns t lzwe we high to low-z [16] 10 ? ns notes 14. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1v/ns or less, timing re ference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 6. 15. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. please see application note an13842 for further clarification. 16. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 17. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the output enters a high impedance state. 18. if both byte enables are toggl ed together, this value is 10 ns. 19. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 8 of 16 switching waveforms figure 1. read cycle 1 (address transition controlled) [20, 21] figure 2. read cycle 2 (oe controlled) [21, 22] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes: 20. the device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 21. we is high for read cycle. 22. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 9 of 16 figure 3. write cycle 1 (we controlled) [23, 24, 25] figure 4. write cycle 2 (ce 1 or ce 2 controlled) [23, 24, 25] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 26 ce 1 address ce 2 we data i/o oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 26 ce 1 address ce 2 we data i/o oe bhe /ble notes 23. the internal write time of the me mory is defined by the overlap of we , ce = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 24. data i/o is high impedance if oe = v ih . 25. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 26. during this period, the i/os are in output state and input signals must not be applied.
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 10 of 16 figure 5. write cycle 3 (we controlled, oe low) [27] figure 6. write cycle 4 (bhe /ble controlled, oe low) [27] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 28 ce 1 address ce 2 we data i/o bhe /ble t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 28 ce 1 address ce 2 we data i/o bhe /ble notes 27. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 28. during this period, the i/os are in output state and input signals must not be applied.
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 11 of 16 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x [29] xx x [29] x [29] high-z deselect/power down standby (i sb ) x [29] lxx x [29] x [29] high-z deselect/power down standby (i sb ) x [29] x [29] x x h h high-z deselect/power down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 )readactive (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high-z (i/o 8 ?i/o 15 ) read active (i cc ) l h h l l h high-z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high-z output disabled active (i cc ) l h h h h l high-z output disabled active (i cc ) l h h h l l high-z output disabled active (i cc ) lhlxlldata in (i/o 0 ?i/o 15 ) write active (i cc ) lhlxhldata in (i/o 0 ?i/o 7 ); high-z (i/o 8 ?i/o 15 ) write active (i cc ) lhlxlhhigh-z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) note 29. the ?x? (don?t care) state for the chip enables and byte enables in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 12 of 16 ordering information speed (ns) ordering code package diagram package type operating range 55 CY62157EV18ll-55bvxi 51-85 150 48-ball very fine pi tch ball grid array (pb-free) industrial contact your local cypress sales represent ative for availability of these parts. ordering code definitions temperature range: i = industrial bvx = 48-ball vfbga (pb-free) xx = speed grade low power voltage range (1.8 v typical) e = process technology 90 nm datawidth = 16 density = 8-mbit family code: mobl sram family company id: cy = cypress cy 55 bvx 621 5 7 e v18 ll i
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 13 of 16 package diagrams figure 7. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 51-85050 *d
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 14 of 16 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory vfbga very fine ball gird array we write enable symbol unit of measure c degrees celsius ? a microamperes ma milliamperes mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts
CY62157EV18 mobl ? document #: 38-05490 rev. *h page 15 of 16 document history document title: CY62157EV18 mobl ? , 8-mbit (512k x 16) static ram document number: 38-05490 rev. ecn no. issue date orig. of change description of change ** 202862 see ecn aju new data sheet *a 291272 see ecn syt converted from advance information to preliminary changed v cc max from 2.20 to 2.25 v changed v cc stabilization time in footnote #7 from 100 ? s to 200 ? s changed i ccdr from 4 to 4.5 ? a changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bins changed t doe from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively changed t hzoe , t hzbe and t hzwe from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns speed bins respectively changed t hzce from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively changed t sce , t aw, and t bw from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins respectively changed t sd from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively added pb-free package information *b 444306 see ecn nxr converted from preliminary to final removed 35 ns speed bin and ?l? bin changed ball e3 from dnu to nc removed redundant footnote on dnu modified maximum ratings spec for supply volt age and dc input voltage from 2.4v to 2.45v changed the i cc typ value from 16 ma to 18 ma and i cc max value from 28 ma to 25 ma for test condition f = fax = 1/t rc changed the i cc max value from 2.3 ma to 3 ma for test condition f = 1mhz changed the i sb1 and i sb2 max value from 4.5 ? a to 8 ? a and typ value from 0.9 ? a to 2 ? a respectively updated thermal resistance table changed test load capacitance from 50 pf to 30 pf added typ value for i ccdr changed the i ccdr max value from 4.5 ? a to 3 ? a corrected t r in data retention characteristics from 100 ? s to t rc ns changed t lzoe from 3 to 5, changed t lzce from 6 to 10, changed t hzce from 22 to 18, changed t lzbe from 6 to 5, changed t pwe from 30 to 35, changed t sd from 22 to 25, and changed t lzwe from 6 to 10 added footnote #13 updated the ordering information and replaced the package name column with package diagram *c 571786 see ecn vkn replaced 45ns speed bin with 55ns *d 908120 see ecn vkn added footnote #7 related to i sb2 added footnote #12 related ac timing parameters *e 2934396 06/03/10 vkn added footnote #23 related to chip enable updated package diagram and template *f 3110053 12/14/2010 pras changed ta ble footnotes to footnotes. added ordering code definitions. *g 3243545 04/28/2011 rame updated as per template . added acronyms and units of measure table. *h 3295175 06/29/2011 rame added i sb1 and i ccdr to footnotes 7 and 11. modified footnote 29 and referenced in truth table .
document #: 38-05490 rev. *h revised june 29, 2011 page 16 of 16 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. CY62157EV18 mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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